The present invention generally relates to the design of logic circuits for use with silicon-on-insulator (SOI) technology, and more particularly, to the use of diode switching elements in such logic circuits.
Conventional or bulk semiconductor transistors are formed in a semiconductor substrate by implanting a well of either P-conductivity or N-conductivity silicon in a silicon substrate wafer of the opposite conductivity. Gates and source/drain diffusions are then manufactured using commonly known processes. These form devices known as metal-oxide-semiconductor (MOS) field effect transistors (FETs). Each of these FETs must be electrically isolated from the others in order to avoid shorting the circuits. These FET""s are typically interconnected through metal layers above the bulk substrate to form logic devices including inverters, inverting switches, NAND gates and others. Typically, the interconnections will be structured to interconnect both P-Channel and N-Channel FET""s in accordance with known complimentary metal oxide semiconductor (CMOS) techniques to minimize power consumption. The logic devices are interconnected to form logic circuits including different degrees of fan-in and fan-out for example.
Diodes theoretically may be used to perform certain functionality in logic circuits. However, bulk semiconductor logic circuits typically do not use diodes. Bulk semiconductor diodes are formed in wells and occupy a surface area equivalent or larger than that of a FET. Furthermore, their capacitive and resistive characteristics increase power consumption and reduce performance (e.g. maximum clock speed) making them inferior to equivalent circuit function utilizing bulk semiconductor FETs. For example, a bulk semiconductor diode 10 shown in FIG. 1 includes an N-conductivity cathode 14 surrounded by P-conductivity anode 12 which is implanted in a N-conductivity well 16 formed in a P-conductivity substrate 18. In operation, a current can flow from the anode 12 to the cathode 14 when diode 10 is forward biased. To obtain proper electrical characteristics, the mechanical geometry of the anode 12, cathode 14 and well 16 are such that the diode 10 is typically larger than a FET.
Even utilizing bulk semiconductor FETs for logic circuits have a drawback in that a relatively large amount of surface area is needed for the electrical isolation of the various FETs. This is undesirable for the current industry goals for size reduction. Additionally, junction capacitance between the source/drain and the bulk substrate and xe2x80x9coffxe2x80x9d state leakage from the drain to the source increase power consumption. Junction capacitance also effects performance in that it slows the speed at which a device using such transistors can operate. These problems result in difficulties in reducing the size, power consumption, and voltage of CMOS technology devices.
There continues to exist a strong continuing need in the art for the reduction in size and power consumption of logic. Accordingly, there is a strong need in the art a logic circuit that provides for reduced size and power consumption over known logic circuits.
A first aspect of this invention is to provide a logic circuit on a substrate having at least one silicon-on-insulator region with a thin semiconductor layer over an insulating layer of buried oxide. A plurality of logic gates are formed in the at least one silicon-on-insulator region and a plurality of silicon on insulator diodes are formed in the at least one silicon-on-insulator region and operatively coupled among at least one of input terminals and output terminals of the plurality of logic gate to control logic state switching among the plurality of logic gates. The logic circuit may further include an output rail wherein at least one silicon on insulator diode is coupled between the output terminal of at least one logic gate and the logic circuit output rail providing a forward biased current path from the logic circuit output rail to the output terminal of the logic gate. The logic circuit may yet further include a switch, driven by a clock signal, coupling the logic circuit output rail to a logic high source when the clock signal is logic low and isolating the logic circuit output rail from the logic high source when the clock signal is logic high. Preferably, the switch is an inverting switch comprising two SOI FETs and the logic gate is a NAND gate including a first input coupled to the clock signal and a second input coupled to a logic circuit input signal. The NAND gate may comprise four field effect transistors and provide for a forward biased current through the SOI diode to sink to ground through at least one of said field effect transistors.
The logic circuit may further include a second NAND gate including a first input coupled to the clock signal and a second input coupled to a second logic circuit input signal, and a second SOI diode coupled between an output terminal of the second NAND gate and the logic circuit output rail providing a forward biased current path from the logic circuit output rail to the output terminal of the second NAND gate. The logic circuit may further yet include an inverter with an input coupled to the logic circuit output rail and having an output that is a logic OR function of the first logic circuit input signal and the second logic circuit input signal.
A second aspect of the present invention is to provide a method of performing a logic calculation on a silicon-on-insulator circuit, the method comprising a) generating a plurality of first signals at the output terminal of a plurality of logic gates; and b) coupling the logic signals to a silicon on insulator switching diode functioning as an open switch to current flow from the output terminal and as a closed switch to enable current flow into the output terminal. The method may further include coupling an output rail to each of the diodes and to a logic high source when a clock signal is logic low and isolating the output rail from the logic high source when the clock signal is logic high, wherein each first signal corresponds to a NAND function of a corresponding one of a plurality of input signals and the clock signal such that the output rail is a logic NOR function of the plurality of input signals. The method may further yet include coupling the output rail to an inverter to generate an output signal that is logic high when the output rail is logic low and is logic low when the output rail is logic high.
A third aspect of the present invention is to provide a method of forming a logic circuit in a silicon-on-insulator wafer comprising forming a plurality of SOI FETs and a plurality of SOI diodes in a thin silicon layer over a buried oxide layer in said wafer, and interconnecting the plurality of SOI FETs and SOI diodes to form a plurality of logic gates with an output coupled to a cathode of each of the plurality of SOI diodes to isolate each of the logic gates from a logic low sink on an anode side of the SOI diode connected thereto and to sink a logic high charge on the anode side of the SOI diode to a logic low sink through the logic gate.
The step of interconnecting the plurality of SOI FETs and SOI diodes may further include coupling the anodes of a plurality the plurality of diodes to an output rail and forming an inverting switch coupling the output rail to a logic high source when a clock signal is logic low and isolating the output rail from the logic high source when the clock signal is logic high. The step of interconnecting the plurality of SOI FETs and SOI diodes may further yet include forming an inverter coupling the output rail to an output port such that the output port is logic high when the output port is logic low and the output port is logic low when the output rail is logic high.
A fourth aspect of the present invention is to provide a logic circuit comprising a substrate having at least one silicon-on-insulator region with a thin semiconductor layer over an insulating layer of buried oxide. A plurality of diodes may be formed in the at least one silicon-on-insulator region, each diode including an anode and a cathode and operating as a logic element between a logic high potential and a logic low potential to: i) pull logic high on the anode to logic low in the event that the cathode is pulled to logic low; and ii) maintain logic high on the cathode independent of whether the anode is pulled to logic low. The logic circuit may further comprise plurality of logic gates formed in the at least one silicon-on-insulator region. The logic gates may be operatively coupled among the plurality of diodes to pull at least one of the anode and the cathode of at least one of the plurality of diodes to at least one of logic high and logic low.